| Popis: |
The g m /I D -based design of analog integrated circuits introduced by Silveira, et al. in 1996 [1] employs an empirical transistor sizing methodology using SPICE-generated lookup tables. In the design of ultra-low-power amplifiers, the iconic plots of g m /I D vs V OV suggest that some devices should be operated deep in weak inversion (e.g., V OV ≃ −0.2V) where gm/ID is near maximum. Performance parameters such as gain, bandwidth, thermal noise, power dissipation, etc., benefit from this choice. However, in applications where small-signal settling time is critical (e.g., precision switched-capacitor circuits), the unity-gain phase margin, PM, is a parameter of paramount importance. PM (i.e., small-signal settling time) vs. V OV (i.e., strong, moderate or weak inversion) design considerations are presented in this paper. The key result is that as the design choice of V OV moves the region of operation from strong to moderate to weak inversion, PM is reduced substantially and settling time is increased dramatically. In addition to new design insights, area-efficient device layout techniques are illustrated that improve performance. |
