Complex 3D CMOS circuits based on a triple-decker cell
| Autor: | B. Hoefflinger, G. Roos |
|---|---|
| Rok vydání: | 1992 |
| Předmět: |
Engineering
business.industry Circuit design Electrical engineering NAND gate Hardware_PERFORMANCEANDRELIABILITY Integrated circuit law.invention Integrated injection logic Logic synthesis CMOS law Logic gate Hardware_INTEGRATEDCIRCUITS Inverter Electrical and Electronic Engineering business Hardware_LOGICDESIGN |
| Zdroj: | IEEE Journal of Solid-State Circuits. 27:1067-1072 |
| ISSN: | 0018-9200 |
| Popis: | Presents circuit design for a three-dimensional (3D) CMOS integrated process. This process, with its three stacked transistor channels, leads to the very efficient basic circuits: inverter, selector, and NAND2. These elements are used to build a complete cell library with standard elements like NORs, latches, flip-flops, etc. Special macro blocks such as multipliers, SRAMs and content addressable memories (CAMs) complete the circuit library. Novel concepts and implementations of three-dimensional prefabricated semicustom arrays are introduced. These are the NAND array and the selector array, for which technology-dependent logic synthesis is investigated. Area requirements for static 3-D CMOS logic ranges from 50% down to 33% compared to two-dimensional (2-D) CMOS. These figures include the wiring and are caused by the transistor stacking and the large number of interconnection layers used in the 3D CMOS process. > |
| Databáze: | OpenAIRE |
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