SELF-TIMED LOOK UP TABLE FOR ULAs AND FPGAs
| Autor: | Y. G. Diachenko, A. Yu. Skornyakova, Sergey F. Tyurin, Yu.A. Stepchenkov |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Computer science
business.industry 010401 analytical chemistry Universal logic 02 engineering and technology General Medicine 01 natural sciences 020202 computer hardware & architecture 0104 chemical sciences Boolean algebra symbols.namesake Logic gate Lookup table Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Redundancy (engineering) symbols Electronics Field-programmable gate array business Computer hardware Hardware_LOGICDESIGN Electronic circuit |
| Zdroj: | Radio Electronics, Computer Science, Control. 1:36-45 |
| ISSN: | 2313-688X 1607-3274 |
| Popis: | Context. Self-Timed Circuits, proposed by D. Muller on the rise of the digital era, continues to excite researchers’ minds. These circuits started with the task of improving performance by taking into account real delays. Then Self-Timed Circuits have moved into the field of green computing. At last, they are currently positioned mainly in the field of fault tolerance. There is much redundancy in Self-Timed Circuits. It is believed that Self-Timed Circuits approaches will be in demand in the nano-circuitry when a synchronous approach becomes impossible. Strictly Self-Timed Circuits check transition process completion for each gate’s output. For this, they use so-called D. Muller elements (C-elements, hysteresis flip-flops, G-flip-flops). Usually, Self-Timed Circuits are designed on Uncommitted Logic Array. Now an extensive base of Uncommitted Logic Array Self-Timed gates exists. It is believed that SelfTimed Circuits are not compatible with FPGA technology. However, attempts to create self-timed FPGAs do not stop. The article proposes a Self-Timed Lookup Table for the Self-Timed Uncommitted Logic Array and the Self-Timed FPGA, carried out either by constants or utilizing additional memory cells. Authors proposed 1,2 – Self-Timed Lookup Table and described simulation results. Objective. The work’s goal is the analysis and design of the Strictly Self-Timed universal logic element based on Uncommitted Logic Array cells and pass-transistors circuits. Methods. Analysis and synthesis of the Strictly Self-Timed circuits with Boolean algebra. Simulation of the proposed element in the CAD “ARC”, TRANAL program, system NI Multisim by National Instruments Electronics Workbench Group, and layout design by Microwind. The reliability theory and reliability calculations in PTC Mathcad. Results. Authors designed, analyzed, and proved the Self-Timed Lookup Table’s workability for the Uncommitted Logic Arrays and FPGAs. Layouts of the novel logic gates are ready for manufacturing. Conclusions. The conducted studies allow us to use proposed circuits in perspective digital devices. |
| Databáze: | OpenAIRE |
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