A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput
| Autor: | Ki-whan Song, Gyo Soo Choo, Kitae Park, Kye-Hyun Kyung, Dae-Seok Byeon, Jisu Kim, Jinbae Bang, Moosung Kim, Lee Kang-Bin, Lee Han-Jun, Seung-Bum Kim, Seonyong Lee, Minyeong Lee, Sung-Min Joe, Jinwon Choi, Jonghoo Jo, Kyung Min Kim, Chulbum Kim, Jeong-Don Lim, Young-Sun Min, Young-don Choi, Joon-Suc Jang, Dongjin Shin, Nahyun Kim, Rho Young-Sik, Park Jiyoon, Jungkwan Kim, Hwajun Jang, Yong-Ha Park, Deokwoo Lee, Young-Hwan Ryu, SeonGeon Lee, Yu Chung-Ho, Ho-joon Kim, Minseok Kim, Jonghoon Park, Hyun-Jin Kim, Seung-Hyun Moon, Seung-jae Lee, Cheon An Lee, Sohyun Park, Minsu Kim |
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| Rok vydání: | 2018 |
| Předmět: |
010302 applied physics
Hardware_MEMORYSTRUCTURES Computer science Nand flash memory 020208 electrical & electronic engineering 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Bit error rate 02 engineering and technology Parallel computing 01 natural sciences Throughput (business) |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2018.8310323 |
| Popis: | Since the first demonstration of a production quality three-dimensional (3D) stacked-word-line NAND Flash memory [1], the 3b/cell 3D NAND Flash memory has seen areal density increases of more than 50% per year due to the aggressive development of 3D-wordline-stacking technology. This trend has been consistent for the last three consecutive years [2-4], however the storage market still requires higher density for diverse digital applications. A 4b/cell technology is one promising solution to increase bit density [5]. In this paper, we propose a 4b/cell 3D NAND Flash memory with a 12MB/s program throughput. The chip achieves a 5.63Gb/mm2 areal density, which is a 41.5% improvement as compared to a 3b/cell NAND Flash memory in the same 3D-NAND technology [4]. |
| Databáze: | OpenAIRE |
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