A high-speed 16-kb GaAs SRAM of less than 5 ns using triple-level metal interconnection
| Autor: | S. Matsue, H. Makino, H. Nakano, K. Nishitani, K. Sumitani, T. Oku, M. Sakai, Minoru Noda, M. Otsubo |
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| Rok vydání: | 1992 |
| Předmět: |
Very-large-scale integration
Interconnection Yield (engineering) Materials science business.industry Electrical engineering Dissipation RC time constant Electronic Optical and Magnetic Materials Hardware_INTEGRATEDCIRCUITS Wafer Static random-access memory Electrical and Electronic Engineering business Access time |
| Zdroj: | IEEE Transactions on Electron Devices. 39:494-499 |
| ISSN: | 0018-9383 |
| Popis: | The authors have realized 16-kb SRAMs with maximum address access time of less than 5 ns and typical power dissipation of less than 2 W at temperatures ranging from 25 degrees C to 100 degrees C. For the RAMs, they have developed a triple-level Au-based interconnection technology that reduces the wiring length and chip size of the SRAM so as to achieve high speed and high yield. Consequently, the wiring length and chip size are reduced to 69% and 58%, respectively, of those obtained by in previous work. The authors experimentally compared the delay time incurred by double-level interconnection and that by triple-level interconnection. This ratio is found to agree well with the simulated one by a model with distributed RC delay. After successfully suppressing Au hillock generation by lowering the process temperature, yield per wafer of 10% is obtained. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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