Review on design of less complex, high speed Viterbi decoders for accurate extraction of message bits
| Autor: | Nandhitha. N.M, B.N. HariChandana, Balamurugan., Yenduri. Bhagyasri |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
021103 operations research
Iterative Viterbi decoding Computer science Real-time computing 0211 other engineering and technologies 020206 networking & telecommunications Data_CODINGANDINFORMATIONTHEORY 02 engineering and technology Viterbi algorithm Computer Science::Hardware Architecture symbols.namesake Computer engineering Viterbi decoder Convolutional code 0202 electrical engineering electronic engineering information engineering symbols Code (cryptography) Literature survey Encoder Soft output Viterbi algorithm Computer Science::Information Theory |
| Zdroj: | 2016 Online International Conference on Green Engineering and Technologies (IC-GET). |
| Popis: | Convolutional encoders and Viterbi decoders are the most commonly used channel encoders/decoders used for efficient extraction of message bits. Convolutional encoder used EXOR gates for generating the code bits. Conventional Viterbi decoders use Trellis diagrams for extracting the message bits. Architecture of Viterbi decoder includes Branch Metric Unit (BMU), Path Metric Unit (PMU) and SurvivorMemory Unit (SMU). Considerable research is carried out in this area to develop efficient architectures that is less complex and uses lesser number of logic units. Also researchers work on reducing the delay time and thereby increasing the speed without compromising the increase in area. In this paper, a detailed literature survey is provided on various techniques used for less complex and high speed design of Viterbi decoders. The design of ANFIS based Viterbi decoder for noise free channel encoding is also described in this paper. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|