| Popis: |
The ability to control the cross-sectional profile of polysilicon gate structures on semiconductor devices is paramount to maximize product yield and transistor performance. Tighter control of gate profile parameters leads to a tighter distribution of transistor speeds, resulting in more optimized and consistent device performance. Furthermore, the ability to correlate physical in-line profile measurements taken at gate patterning process steps, to back-end-of-line device parametric test results, enables semiconductor manufacturers to minimize the cost per good die produced, by accurately screening out-of-spec product early in the process flow. The significant increase in the number of chips on today's 300mm wafers heightens the importance of obtaining reliable in-line data. In addition, the reduction of design rules to 130nm and below is driving precision requirements on metrology to |
