Design and Optimization of Transparency-Based TAM for SoC Test
| Autor: | Tomokazu Yoneda, Hideyuki Ichihara, Akiko Shuto, Hideo Fujiwara, Tomoo Inoue |
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| Rok vydání: | 2010 |
| Předmět: |
Mathematical optimization
Linear programming Computer science Design for testing Data flow diagram Artificial Intelligence Hardware and Architecture Transparency (graphic) Computer Vision and Pattern Recognition Relaxation (approximation) Electrical and Electronic Engineering Integer programming Algorithm Software Test data |
| Zdroj: | IEICE Transactions on Information and Systems. :1549-1559 |
| ISSN: | 1745-1361 0916-8532 |
| Popis: | We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work. |
| Databáze: | OpenAIRE |
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