A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP
| Autor: | J. Sweet, Chris Nicol, Asawaree Kalavade, J. Williams, Christopher J. Terman, S.J. Daubert, E. Micca, Kanwar Jit Singh, Bryan D. Ackland, E. Sackinger, M. Moturi, D. Brinthaupt, Jay Henry O'neill, J. Othmer, A. Anesko, J. Knobloch |
|---|---|
| Rok vydání: | 2000 |
| Předmět: |
Hardware_MEMORYSTRUCTURES
Coprocessor Reduced instruction set computing CPU cache business.industry Computer science Multiprocessing computer.software_genre Memory controller MIMD Shared memory Embedded system Synchronization (computer science) Operating system Cache Electrical and Electronic Engineering business Semaphore computer Real-time operating system |
| Zdroj: | IEEE Journal of Solid-State Circuits. 35:412-424 |
| ISSN: | 1558-173X 0018-9200 |
| DOI: | 10.1109/4.826824 |
| Popis: | An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PEs are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 200-mm/sup 2/, 0.25-/spl mu/m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|