FPGA Accelerator of Algebraic Quasi Cyclic LDPC Codes for nand Flash Memories

Autor:	Guido Masera, Maurizio Martina, Syed Azhar Ali Zaidi, Abuduwaili Tuoheti
Rok vydání:	2016
Předmět:	010302 applied physics Hardware_MEMORYSTRUCTURES business.industry Computer science Concatenated error correction code NAND gate Data_CODINGANDINFORMATIONTHEORY 02 engineering and technology Serial concatenated convolutional codes Parallel computing 01 natural sciences 020202 computer hardware & architecture Flash (photography) Hardware and Architecture 0103 physical sciences 0202 electrical engineering electronic engineering information engineering Turbo code Forward error correction Electrical and Electronic Engineering Low-density parity-check code business Field-programmable gate array Software Computer hardware
Zdroj:	IEEE Design & Test. 33:77-84
ISSN:	2168-2364 2168-2356
Popis:	In this article, the authors implement an FPGA simulator that accelerates the performance evaluation of very long QC-LDPC codes, and present a novel 8-KB LDPC code for NAND flash memory with better performance.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::b77cbe4e296d5d528a5900b47bf7a0d4 https://doi.org/10.1109/mdat.2015.2497322 Zobrazit plný text záznamu