Heterogeneous architecture models for interconnect-motivated system design
| Autor: | James D. Meindl, Sek M. Chai, D.S. Wills, Tarek M. Taha |
|---|---|
| Rok vydání: | 2000 |
| Předmět: |
Very-large-scale integration
Engineering business.industry Distributed computing Locality Integrated circuit layout Hardware and Architecture Embedded system Systems design System on a chip Electrical and Electronic Engineering Architecture business Engineering design process Software Software architecture description |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8:660-670 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/92.902260 |
| Popis: | On-chip interconnect demand is becoming the dominant factor in modern processor performance and must be estimated early in the design process. This paper presents a set of heterogeneous architectural models that combines architecture description and Rent's rule-based wiring models. These architecture models allow flexible heterogeneous system specifications, enabling investigations of prospective designs in different technology scenarios. Comparisons against actual data demonstrate the models' effectiveness for architecture explorations with highly accurate estimations of local and global wiring demand, as well as chip area and cycle time. Simulation of two candidate system designs reveal trends in interconnect delay with increasing architectural complexity, and confirm the need for high computational locality and short global wires for future architectures. |
| Databáze: | OpenAIRE |
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