Built-in Self-Calibration and Digital-Trim Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL
| Autor: | Bertan Bakkaloglu, Shankar Thirunakkarasu |
|---|---|
| Rok vydání: | 2015 |
| Předmět: |
Engineering
business.industry Capacitive sensing Electrical engineering Linearity Successive approximation ADC Hardware_PERFORMANCEANDRELIABILITY Converters Signal law.invention Capacitor Least significant bit Hardware and Architecture law Hardware_INTEGRATEDCIRCUITS Electronic engineering Electrical and Electronic Engineering business Error detection and correction Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:916-925 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2014.2321761 |
| Popis: | Several state-of-the-art monitoring and control systems, such as dc motor controllers, power line monitoring and protection systems, instrumentation systems, and battery monitors, require direct digitization of high-voltage (HV) input signals. Analog-to-digital converters (ADCs) that can digitize HV signals require high linearity and low-voltage coefficient capacitors. A built-in self-calibration and digital-trim algorithm correcting static mismatches in capacitive digital-to-analog converter (DAC) used in successive approximation register analog-to-digital converters (SAR ADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit HV input range SAR ADC with integrated DEC capacitors. The IC is fabricated in 0.6- $\mu $ m HV-compliant CMOS process, accepting up to $24V_{\rm pp}$ differential input signal. The proposed approach achieves 73.32-dB signal-to-noise and distortion ratio, which is an improvement of 12.03 dB after self-calibration at 400-kS/s sampling rate, consuming 90 mW from a ±15 V supply. The calibration circuitry occupies 28% of the capacitor DAC and consumes $^{2}$ . |
| Databáze: | OpenAIRE |
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