| Popis: |
Next generation 5G standards operating at sub-6GHz and millimeter-wave frequencies place stringent requirements on the design of analog-to-digital converters (ADCs) via conversion speed, ENOB, and power consumption. The reduction of supply voltages through increasingly scaled CMOS process nodes further complicates the design process of these circuits. This work presents a 1GS/s sampling based voltage-to-time converter (VTC) in 65nm process with full 2V pk-pk,diff input range at only 1mW power consumption. We propose a method for tunable distortion compensation across corners to realize a truly robust design. The proposed design has a low frequency figure-of-merit (FOM) of 3.8 fj/conv-step and a high frequency FOM of 2.46 fj/conv-step. The performance of VTC enables realization of time-to-digital converters (TDC) with high resolutions. |
