A Wafer-level System Integration Technology Incorporates Heterogeneous Devices
| Autor: | Hiroshi Yamada, Yutaka Onozuka, Kazuhiko Itaya, Atsuko Iida, Hideyuki Funaki |
|---|---|
| Rok vydání: | 2012 |
| Předmět: |
Materials science
business.industry Process (computing) Electrical engineering Hardware_PERFORMANCEANDRELIABILITY Substrate (printing) visual_art Automotive Engineering Electronic component Hardware_INTEGRATEDCIRCUITS Electronic engineering visual_art.visual_art_medium Interposer System integration Wafer Redistribution layer Layer (object-oriented design) business |
| Zdroj: | International Symposium on Microelectronics. 2012:000793-000800 |
| ISSN: | 2380-4505 |
| DOI: | 10.4071/isom-2012-wp16 |
| Popis: | A pseudo-SoC technology incorporating heterogeneous devices has been developed by applying a wafer-level system integration technology. The pseudo-SoC is set up to realize one microchip with heterogeneous devices made by using individual processes for epoxy resin, insulating layer and redistribution layer, respectively. The individual heterogeneous devices are embedded in the epoxy resin to reconfigure the integration wafer. As the insulating layer and redistribution layer are formed by semiconductor wafer process without interposer substrate, the pseudo-SoC enables integration density and signal transmission speed as identical to that of SoC. Also, as the commercial LSI devices and peripheral passive components are able to use for the system integration, the pseudo-SoC enables reduction of time-to-market as identical that of SiP. This paper describes the heterogeneous devices integration technologies and focuses on the pseudo-SoC that overcomes the limitation of system integration and provides the complementary advantages of SiP and SoC with various applications. |
| Databáze: | OpenAIRE |
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