Fabrication and RTN characteristics of gate-all-around poly-Si junctionless nanowire transistors
| Autor: | Pei-Wen Li, Yung-Chen Chen, Horng-Chih Lin, Ruey-Dar Chang, Tiao-Yuan Huang, Chen-Chen Yang |
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| Rok vydání: | 2016 |
| Předmět: |
010302 applied physics
Fabrication Materials science business.industry Transconductance Transistor Nanowire Nanotechnology 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Noise (electronics) law.invention law Logic gate 0103 physical sciences MOSFET Optoelectronics 0210 nano-technology business Lithography |
| Zdroj: | 2016 IEEE Silicon Nanoelectronics Workshop (SNW). |
| DOI: | 10.1109/snw.2016.7577987 |
| Popis: | Short-channel gate-all-around (GAA) poly-Si junctionless (JL) nanowire (NW) transistors were fabricated using the control available through cost-effective I-Line lithographic patterning and spacer techniques. This scheme enables the production of GAA JL poly-Si NW transistors with channel length of as short as 120 nm and effective width of 49 nm, featuring significant improvement in subthreshold swing (SS) and transconductance (G m ). The shrunken channel allows us to monitor clear random telegraph noise (RTN) signals under a sufficiently large gate overdrive condition. |
| Databáze: | OpenAIRE |
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