Autor:	Larry Layton, Lionel J. Riviere-Cazaux, Nishath Verghese, Bala Kasthuri, Philippe Hurat
Rok vydání:	2009
Předmět:	Standard cell Logic synthesis Computer science Process (computing) Integrated circuit design Increased tolerance Lithography Design for manufacturability Reliability engineering
Zdroj:	SPIE Proceedings.
ISSN:	0277-786X
DOI:	10.1117/12.813969
Popis:	To address the variability challenges inherent to 45 and 32nm as early as possible, a model-based variability analysis has been implemented to predict lithography induced electrical variability in standard cell libraries, and this analysis was used optimize the cell layout and decrease variability by up to 40%.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a65ed597285b04ef9421a5361be2c757 https://doi.org/10.1117/12.813969 Zobrazit plný text záznamu