A 9.95–11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS

Autor:	M.H. Eskiyerli, Sivanendra Selvanayagam, Jack Kenney, Eric Evans, Declan M. Dalton, B. Hilton, T. Kwok, Lawrence M. Devito, D. Hitchcox, V. Reddy, C. McQuilkin, P. Shepherd, Ward S. Titus, D. Mulcahy
Rok vydání:	2006
Předmět:	Phase-locked loop Engineering XFP transceiver CMOS business.industry Delay-locked loop Electronic engineering Electrical and Electronic Engineering Transceiver Serializer business Phase detector Jitter
Zdroj:	IEEE Journal of Solid-State Circuits. 41:2901-2910
ISSN:	0018-9200
DOI:	10.1109/jssc.2006.884344
Popis:	A 9.95-11.3-Gb/s transceiver in 0.13-mum CMOS for XFP modules is presented. The CDR uses a dual-loop DLL/PLL with a binary phase detector to exceed XFP jitter specifications. The dual loop solves the problem of having a controlled jitter transfer bandwidth with a binary phase detector. A half rate binary phase detector with a 2:1 serializer implements full-rate I/O. Dispersion jitter from 12'' of FR4 is equalized resulting in system JGEN under 4 mUIRMS and 35 mUI PP. Power consumption is 800 mW
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::a64ef4857e3a864b7a8699297786a8c6 https://doi.org/10.1109/jssc.2006.884344 Zobrazit plný text záznamu