An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors
| Autor: | Seyed Ghassem Miremadi, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Zahra Azad |
|---|---|
| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Random access memory Multi-core processor Hardware_MEMORYSTRUCTURES Computer science business.industry 02 engineering and technology Parallel computing Energy consumption 01 natural sciences 020202 computer hardware & architecture Tag RAM Computational Theory and Mathematics Hardware and Architecture Embedded system 0103 physical sciences Signal Processing 0202 electrical engineering electronic engineering information engineering Static random-access memory Cache business |
| Zdroj: | IEEE Transactions on Parallel and Distributed Systems. 28:1564-1577 |
| ISSN: | 1045-9219 |
| Popis: | Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems to be the most promising alternative. With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches. High probability of write error due to stochastic switching is a major problem in STT-RAMs. Conventional Error-Correcting Codes (ECCs) impose significant area and energy consumption overheads to protect STT-RAM caches. These overheads in multi-core processors with large last-level caches are not affordable. In this paper, we propose Asymmetry-Aware Protection Technique (A $^2$ PT) to efficiently protect the STT-RAM caches. A $^2$ PT benefits from error rate asymmetry of STT-RAM write operations to provide the required level of cache protection with significantly lower overheads. Compared with the conventional ECC configuration, the evaluation results show that A $^2$ PT reduces the area and energy consumption overheads by about 42 and 50 percent, respectively, while providing the same level of protection. Moreover, A $^2$ PT decreases the number of bit switching in write operations by 28 percent, which leads to about 25 percent saving in write energy consumption. |
| Databáze: | OpenAIRE |
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