| Autor: |
Guido Koerner, Hans-Jürgen Engelmann, H. Nii, Martin Gerhardt, Andy Wei, Hartmut Ruelke, L. T. Su, Mukesh Khare, Manfred Horstmann, Rolf Stephan, O. Herzog, Ralf Otterbach, Judson R. Holt, Dureseti Chidambarrao, Peter Javorka, Helmut Bierstedt, C. Reichel, P. Hubler, Heike Salz, J. Hontschel, H. Chen, Thorsten Kammler, Dominic J. Schepis, A. Hellmich, T. Sato, Woo-Hyeong Lee, N. Kepler, S. Liming, David M. Fried, Matthias Schaller, Michael Raab, Thomas Feudel, D. Greenlaw, Shih-Fen Huang, John Pellerin, Kai Frohberg, A. Neu, Patrick Press, J. Klais, Siddhartha Panda, Andrew Waite, K. Hempel, Markus Lenski, Bernhard Trui, Jörg Hohage, K. Rim, M. Trentsch |
| Rok vydání: |
2005 |
| Předmět: |
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| Zdroj: |
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.. |
| Popis: |
An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different stress techniques are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by 53% and 32%, respectively. This improvement results in 40% higher product speed. To demonstrate the extendibility for future transistor nodes the stress improvements were increased further resulting in record PMOS performance of IDSAT=860muA/mum at 200nA IOFF (self-heating corrected) and 1V. The stress techniques are proven in AMD's 90nm manufacturing processes, and have been scaled for use in 65nm manufacturing |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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