13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applications

Autor: Khoa Minh Nguyen, Muhammad Faisal, Hyung Seok Kim, Satoshi Suzuki, Paolo Madoglio, Amr Fahim, Yorgos Palaskas, Zhichao Zhang, Hongtao Xu, Tan Yulin, Luis Cuellar, Stefano Pellerano, Jianyong Xie, Yanjie Wang, Kailash Chandrashekar, Parmoon Seddighrad, Ashoke Ravi, Divya Shree Vemparala, Thomas A. Tetzlaff, Brent Carlton, William Yee Li, Vaibhav Vaidya
Rok vydání: 2017
Předmět:
Zdroj: ISSCC
DOI: 10.1109/isscc.2017.7870343
Popis: To benefit from Moore's law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are required, increasing system cost and form-factor. Traditional radio architectures require extensive use of high-quality passives, which might use large silicon area or not be available due to process limitations. Fast time to market also demands quicker design cycles, where extensive use of standard digital cells and even automated place-and-route tools for layout is preferred [1]. The proposed transmitter leverages a polar architecture with synthesized digital-to-time converter (DTC) wideband phase modulator, an all-digital PLL and a digital PA with matching network implemented on a flip-chip package to enable single-chip integration in 14nm trigate/finFET technology for IoT and wearable SoCs.
Databáze: OpenAIRE