| Autor: |
S. Takano, Noriyuki Tanino, S. Matsue, Minoru Noda, S. Kayano, H. Makino, K. Nishitani |
| Rok vydání: |
2003 |
| Předmět: |
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| Zdroj: |
10th Annual IEEE (GaAs IC) Symposium, Gallium Arsenide Integrated Circuit. Technical Digest 1988.. |
| Popis: |
The authors describe a GaAs 1 K*4 static random-access memory (SRAM) which has been designed using a novel circuit technology to reduce the scattering and the temperature dependence of the access time. To reduce the subthreshold leakage current in the access transistors of the unselected memory cells, the baselines connected to the unselected memory cells were raised from the ground level. The 4-Kb SRAM was fabricated using 1.0- mu m self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75 degrees C. Little change in the address access time was observed over 0 to 75 degrees C. > |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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