Effect of Silicon Thickness on Contact-Etch-Stop-Layer-Induced Silicon/Buried-Oxide Interface Stress for Partially Depleted SOI
| Autor: | Che-Hua Hsu, Chien-Ting Lin, Wen-Kuan Yeh, M. Ma, Tung-Hsing Lee, Yean-Kuen Fang, Liang-Wei Chen, Li-Wei Cheng, Ming-Shing Chen |
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| Rok vydání: | 2006 |
| Předmět: |
Materials science
Silicon business.industry Electrical engineering Silicon on insulator chemistry.chemical_element Strained silicon Electronic Optical and Magnetic Materials Stress (mechanics) Strain engineering chemistry MOSFET Optoelectronics Electrical and Electronic Engineering Thin film business Layer (electronics) |
| Zdroj: | IEEE Electron Device Letters. 27:963-965 |
| ISSN: | 0741-3106 |
| DOI: | 10.1109/led.2006.886715 |
| Popis: | In this letter, based on both experimental investigations and simulation confirmation, it was found that a strained contact etch stop layer over the thin silicon layer of a partially depleted silicon-on-insulator (PD-SOI) will induce high stress on the buried-oxide/silicon interface. Additionally, the interface stress increases with decrease of silicon thickness TSI, thus enhancing the current of the MOSFET, e.g., as TSI shrinks from 90 to 50 nm, current enhancement for PD-SOI n-channel MOS increased from 7% to 12% due to the increase of interface stress. The results are expected to be more significant for devices with thinner TSI such as fully depleted silicon-on-insulator and multigate devices |
| Databáze: | OpenAIRE |
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