Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks
| Autor: | Minkyu Kim, Tushar Gupta, Mingoo Seok, Shihui Yin, Zhewei Jiang, Jae-sun Seo |
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| Rok vydání: | 2020 |
| Předmět: |
Digital electronics
Random access memory Dataflow business.industry Computer science Deep learning Bottleneck Computer architecture Application-specific integrated circuit Hardware and Architecture In-Memory Processing System on a chip Static random-access memory Artificial intelligence Electrical and Electronic Engineering business Software |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:48-61 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2019.2940649 |
| Popis: | To enable essential deep learning computation on energy-constrained hardware platforms, including mobile, wearable, and Internet of Things (IoT) devices, a number of digital ASIC designs have presented customized dataflow and enhanced parallelism. However, in conventional digital designs, the biggest bottleneck for energy-efficient deep neural networks (DNNs) has reportedly been the data access and movement. To eliminate the storage access bottleneck, new SRAM macros that support in-memory computing have been recently demonstrated. Several in-SRAM computing works have used the mix of analog and digital circuits to perform XNOR-and-ACcumulate (XAC) operation without row-by-row memory access and can map a subset of DNNs with binary weights and binary activations. In the single array level, large improvement in energy efficiency (e.g., two orders of magnitude improvement) has been reported in computing XAC over digital-only hardware performing the same operation. In this article, by integrating many instances of such in-memory computing SRAM macros with an ensemble of peripheral digital circuits, we architect a new DNN accelerator, titled Vesti . This new accelerator is designed to support configurable multibit activations and large-scale DNNs seamlessly while substantially improving the chip-level energy-efficiency with favorable accuracy tradeoff compared to conventional digital ASIC. Vesti also employs double-buffering with two groups of in-memory computing SRAMs, effectively hiding the row-by-row write latencies of in-memory computing SRAMs. The Vesti accelerator is fully designed and laid out in 65-nm CMOS, demonstrating ultralow energy consumption of $ for CIFAR-10 classification at 1.0-V supply. |
| Databáze: | OpenAIRE |
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