A PA-RISC microprocessor PA/50L for low-cost systems
| Autor: | M. Kainaga, H. Takewa, M. Yamagami, Hirokazu Aoki, Norio Nakagawa, K. Yamada, T. Funabashi, Tetsuhiko Okada, Makoto Satoh, Nobuyuki Hayashi, S. Fujiwara, M. Asai, Susumu Narita, H. Takeda, Osamu Nishii, Kunio Uchiyama, Noriharu Hiratsuka, S. Matsuo, Junichi Nishimoto |
|---|---|
| Rok vydání: | 2002 |
| Předmět: |
Instruction prefetch
ComputerSystemsOrganization_COMPUTERSYSTEMIMPLEMENTATION Reduced instruction set computing Computer science business.industry ComputerSystemsOrganization_PROCESSORARCHITECTURES computer.software_genre FLOPS law.invention Microprocessor law Dhrystone Operating system Cache business computer Inner loop Computer hardware |
| Zdroj: | COMPCON |
| DOI: | 10.1109/cmpcon.1994.282946 |
| Popis: | The PA/50L is a low-cost, low-power microprocessor from Hitachi Ltd. that is fully compatible with the PA-RISC architecture 1.1, third edition. This microprocessor achieves 55 VAX MIPS (Dhrystone 1.1), 10.6 MFLOPS (LINPACK inner loop) and 1.3 W at 33 MHz. In order to achieve high performance with no external cache, a non-blocking cache and a data prefetch instruction are provided. This paper gives an overview of the microprocessor and describes its capabilities. > |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|