Autor: |
P.C. Yen, L.D. Chen, R.C.J. Wang, Kuei-Shu Chang-Liao, C.C. Chiu, K. Wu, S.R. Lin |
Rok vydání: |
2005 |
Předmět: |
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Zdroj: |
Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005.. |
Popis: |
Stress-induced voiding (SIV) was studied in the aspects of global and localized stress variation with the change of copper geometries. Two types of interconnect structures were adopted to evaluate resistance shift versus bake time and feature size effect in Cu/low-k systems. A 3D modeling of finite element analysis (FEA) was conducted to profile the stress contour, which directly attributed to the copper voiding underneath via as well as inside via. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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