| Popis: |
The fan-out panel-level chip-last packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, and fabrication of: (a) the heterogeneous integration of one large chip and one small chip with 50µm-pitch (minimum), (b) a fine metal linewidth (L) and spacing (S) redistribution-layer (RDL)-first substrate on a temporary glass carrier, (c) an ordinary build-up package substrate on a panel, (d) a hybrid substrate which is by soldering the RDL-substrate on top of the build-up substrate, and (e) the chips to hybrid substrate bonding and underfilling. Reliability assessment by thermomechanical simulation includes thermal cycling of the heterogeneous integration of the two-chip package on the hybrid substrate that is performed by a nonlinear temperature- and time-dependent finite-element analysis. |
