A new approach to Programmable Logic Array for single-clock CMOS
| Autor: | Minglun Gao, Yong-Sheng Yin, Cong Liu |
|---|---|
| Rok vydání: | 2006 |
| Předmět: |
Very-large-scale integration
Computer science business.industry Macrocell array Programmable logic array Programmable logic device Programmable Array Logic CMOS Embedded system Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering business Field-programmable gate array Simple programmable logic device Hardware_LOGICDESIGN |
| Zdroj: | Journal of Electronics (China). 23:157-160 |
| ISSN: | 1993-0615 0217-9822 |
| DOI: | 10.1007/s11767-005-0026-9 |
| Popis: | Programmable Logic Array (PLA) is an important building circuit of VLSI chips and some of the FPGA architectures have evolved from the basic PLA architectures. In this letter, a dynamic and static mixed PLA with single-phased clock is presented. Combining both dynamic and static design style rather than introducing additional interface-buffers overcomes the racing problem, thereby saves the chip area. Besides inheriting the advantages of dynamic circuit—low power dissipation and compact structure, this approach also provides high-speed operation. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
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