Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis
| Autor: | Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton |
|---|---|
| Rok vydání: | 2021 |
| Předmět: |
Very-large-scale integration
Computer science business.industry 02 engineering and technology Integrated circuit Chip 020202 computer hardware & architecture law.invention Reduction (complexity) Software Memory management Computer engineering law 0202 electrical engineering electronic engineering information engineering 020201 artificial intelligence & image processing Computerized adaptive testing business Cluster analysis |
| Zdroj: | VTS |
| Popis: | Logic diagnosis is a software-based methodology to identify the behavior and location of defects in failing integrated circuits, which is an essential step in yield learning. Conventionally, accurate diagnosis requires a sufficient amount of failing data, indicating a high test cost. Prior work that attempt to solve this problem either use a fixed pattern order, ignoring the characteristics of each chip, or require significant memory which leads to unacceptable increases in test cost. In this work, a new algorithm is described for dynamically selecting the test pattern order that leads to significant reduction in memory cost. Experiments using two industrial chips demonstrate the efficacy of the approach. Compared to prior work, the algorithm described in this work uses as little as 1/500 of tester space to store failing data. |
| Databáze: | OpenAIRE |
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