ASIC implementation of high speed fast fourier transform based on Split-radix algorithm
| Autor: | Lyla B Das, Nandyala Ramanatha Reddy, Sriharsha Enjapuri, A. Rajesh |
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| Rok vydání: | 2014 |
| Předmět: |
Cooley–Tukey FFT algorithm
Signal processing Multidimensional signal processing Split-radix FFT algorithm business.industry Computer science Prime-factor FFT algorithm Fast Fourier transform Filter (signal processing) Hardware_ARITHMETICANDLOGICSTRUCTURES business Algorithm Digital signal processing |
| Zdroj: | 2014 International Conference on Embedded Systems (ICES). |
| DOI: | 10.1109/embeddedsys.2014.6953043 |
| Popis: | Mathematical applications such as DFT and convolution are two main and common operations in signal processing applications. Many other Signal processing algorithms such as filter, spectrum estimation and OFDM can be transformed into DFT to implement in hardware. FFT is the collection of group of algorithms that performs the DFT at higher speed. FFT is indispensable in most signal processing applications, so the designing of an appropriate algorithm for the implementation of FFT can be most important in Most of the digital signal processing. The techniques such as pipelining and parallel calculations have potential impacts on VLSI implementation of FFT algorithm. By theoretical observations Split-radix algorithm is an appropriate algorithm for the implementation of FFT among all the effective algorithms of FFT, because it reduces number of arithmetic operations to great extent. At the requirement of high speed, an algorithm that is best for high speed implementation is to be found. This algorithm performs well in the implementation of FPGA and ASIC, satisfies the requirement of high speed. |
| Databáze: | OpenAIRE |
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