| Autor: |
Kazutaka Ikegami, Saori Kashiwada, S. Fujita, Hiroyuki Hara, Y. Kato, Yasuo Unekawa, Keiko Abe, Daisuke Saida, Ito Junichi, Eiji Kitagawa, Keiichi Kushida, Hiroki Noguchi, Chikayoshi Kamata, Naoharu Shimomura, Atsushi Kawasumi |
| Rok vydání: |
2013 |
| Předmět: |
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| Zdroj: |
2013 5th IEEE International Memory Workshop. |
| DOI: |
10.1109/imw.2013.6582102 |
| Popis: |
Circuit techniques for energy-efficient STT MRAM, which is suitable for replacing SRAM L2 cache memories, are proposed. The waking-up from the power-down mode without any cycle penalties becomes possible by eliminating the voltage generator even at higher frequency than 100MHz. The read current variation caused by the generator elimination is mitigated by 50% using the adaptive pulse-driven read current control. The cross-coupled hierarchical switch reduces the unneeded read current by 66% and enhances the read margin. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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