A CMOS low-power multiple 2.5-3.125-Gb/s serial link macrocellfor high IO bandwidth network ICs

Autor:	J.H. O'Neill, D. Inglis, J. Othmer, Fuji Yang
Rok vydání:	2002
Předmět:	Engineering business.industry Chip Phase-locked loop CMOS Phase noise Hardware_INTEGRATEDCIRCUITS Electronic engineering Macrocell Electrical and Electronic Engineering Transceiver business Clock recovery Jitter
Zdroj:	IEEE Journal of Solid-State Circuits. 37:1813-1821
ISSN:	1558-173X 0018-9200
DOI:	10.1109/jssc.2002.804341
Popis:	This paper presents an 8-channel 2.5–3.125-Gb/s/ch serial link transceiver that achieves a total IO bandwidth of 20 Gb/s with a power consumption of less than 685 mW. The macrocell uses a shared phase-locked loop (PLL) architecture to minimize the potential noise coupling from the core digital part. The clock recovery is based on a new four-quadrant analog phase interpolator to overcome the phase discontinuity in a traditional analog quadrature-phase mixing interpolator. A dynamic amplitude control algorithm is used to maintain the loop stability while maximizing the interpolator?s output. The receiver is constructed using half-rate integrate-and-dump devices to eliminate the requirement of quadrature clock and to improve the receiver sensitivity. A PMOS transmitter driver is used, so that its output voltage referenced to the ground is independent of power supply voltage. On-chip clock generation PLLs are implemented to provide global half-rate clocks. The prototype chip fabricated in a 0.16-μm CMOS process is under a 1.5-V power supply. The measured recovered clock jitter is 87 ps, peak-to-peak. The transmitter's output jitter is 58 ps, peak-to-peak. The active area of the macrocell is about 2 mm2.
Databáze:	OpenAIRE
Externí odkaz:	https://explore.openaire.eu/search/publication?articleId=doi_________::83ff4486eaf13a9b49ebbfeb728809a2 https://doi.org/10.1109/jssc.2002.804341 Zobrazit plný text záznamu