Thermal performance analysis of a 3D package
| Autor: | Siow Pin Melvin Tan, Keng Hwa Teo, Xiaowu Zhang, Fa Xing Che, Damaruganath Pinjala, Yen Yi Germaine Hoe, S. Gao |
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| Rok vydání: | 2010 |
| Předmět: |
Materials science
business.product_category business.industry Thermal resistance Electrical engineering Mechanical engineering Hardware_PERFORMANCEANDRELIABILITY Thermal conduction Thermal design power System in package Heat spreader Hardware_INTEGRATEDCIRCUITS Die (manufacturing) Junction temperature Integrated circuit packaging business |
| Zdroj: | 2010 12th Electronics Packaging Technology Conference. |
| DOI: | 10.1109/eptc.2010.5702608 |
| Popis: | Three dimensional integrated circuits offer significant advantages over single chip packages in terms of functionalities and footprint needed. A key technology to enable the adoption of these advanced packages in electronic systems is Through-Silicon-Via (TSV). The use of TSV has realized integration in the vertical domain. However, as more dies are stacked within the package, the heat generated has to travel a longer distance across many interfaces to reach the cooling solution exterior to the package. This poses a limit on the number of dies and the heat dissipation limits that can be used on the dies. The work reported here investigated the thermal performance of a typical stacked package configuration, comprising of 6 memory dies on top of a logic die. The thermal model is generated by decoupling the different length scales involved into system, package and die level. At the system level, different cooling solutions for a maximum thermal design power of 6 W that can be adopted for mobile applications were analyzed. Different stacking configurations and die power allocation were considered to look at the best layout for lowest junction temperature by using an Elmore-delay model. Results from the system level thermal modeling showed that a viable cooling solution for mobile application is micro heatpipes technology. When it is coupled with a heat spreader to the external polycarbonate casing, a temperature rise of 38.1°C is seen. Compared to conduction via PCB, the micro heatpipe cooling solution is able to reduce the temperature rise by 71%. Using the Elmoredelay model, general thermal design guidelines were generated for the die heat dissipation and location in the stacked package. It is also found out that stacking less dies of higher heat load is better than stacking more dies with lower power. On the memory die, maximum junction temperature of 74°C within the 400 µm pitch microbumps is seen. On the processor die, the junction temperature is 78°C and is located at the middle of the die. |
| Databáze: | OpenAIRE |
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