$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS
| Autor: | Hiroki Noguchi, Miyoshi Fukumoto, Megumi Yakabe, Tadaomi Daibou, Shinobu Fujita, Junichi Ito, Saori Kashiwada, Shinji Miwa, Yoshishige Suzuki, Keiko Abe, Daisuke Saida |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Magnetoresistive random-access memory Materials science Magnetoresistance business.industry CPU cache Transistor Electrical engineering 02 engineering and technology 021001 nanoscience & nanotechnology 01 natural sciences Electronic Optical and Magnetic Materials law.invention Magnetization CMOS law 0103 physical sciences Optoelectronics Cache Electrical and Electronic Engineering Data retention 0210 nano-technology business |
| Zdroj: | IEEE Transactions on Electron Devices. 64:427-431 |
| ISSN: | 1557-9646 0018-9383 |
| DOI: | 10.1109/ted.2016.2636326 |
| Popis: | Magnetization switching is confirmed for sub-3-ns pulses below $100~\mu \text{A}$ in perpendicular magnetic tunnel junctions (MTJs) down to 16 nm in diameter. The magnetoresistance ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of −6 (10−6) are demonstrated. Read and write current margins, which are important device designs, are sufficiently large to avoid read disturbances. Moreover, $1\times $ -to- $2\times $ -nm MTJs have sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remains stable after 1012 write events. To the best of our knowledge, this is the first demonstration of $1\times $ - to $2\times $ -nm MTJs supporting cache memory along with read–write current margins, fast read operations, low power consumption, sufficient retention, and high endurance. |
| Databáze: | OpenAIRE |
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