An Incremental Placement Flow for Advanced FPGAs With Timing Awareness
| Autor: | Jun Yu, Yanyue Xie, Jianli Chen, Zhifeng Lin, Peng Zou, Sifei Wang |
|---|---|
| Rok vydání: | 2022 |
| Předmět: |
Computer science
business.industry Circuit performance Flow (psychology) Packing algorithm Timing closure Computer Graphics and Computer-Aided Design Embedded system Hardware_INTEGRATEDCIRCUITS Electrical and Electronic Engineering Routing (electronic design automation) business Field-programmable gate array Critical path method Software Electronic circuit |
| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41:3092-3103 |
| ISSN: | 1937-4151 0278-0070 |
| DOI: | 10.1109/tcad.2021.3120070 |
| Popis: | As interconnects dominate circuit performance in modern FPGAs, placement becomes a crucial stage for timing closure. Traditional FPGA placers seldom consider the timing constraints, and thus may lead to illegal routing solutions. In this paper, we present an incremental timing-driven placement flow for advanced FPGAs. First, a timing-based global placement strategy is designed to guide heterogeneous blocks to desired locations with satisfied timing constraints. Then, a timing-aware packing algorithm is developed to mitigate the design complexity while improving the timing results. Finally, we propose a critical path-based optimization method to generate optimized layout without timing violations. We evaluate our algorithm based on industrial circuits using an advanced FPGA device. The experimental results show that our placer achieves an 5.1% improvement in worst slack, and produces placements that require 16.7% less time to route when compared with the leading commercial tool Xilinx Vivado. |
| Databáze: | OpenAIRE |
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