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A research on VLSI Floor planning’s physical layout is addressed using optimization methods to improve VLSI chip efficiency. VLSI floor planning is regarded as a non-polynomial issue. Calculations can solve such issues. Representation of floorplan is the basis of this process. The depictions of the floor plan demonstrate more effect on search space as well as the design complexity of the floor plan. This article aims at exploring various algorithms which add to the issue of managing alignment limitations such as excellent positioning, optimal region and brief run time. Many scientists are proposing and suggesting diverse heuristic algorithms and also distinct metaheuristic algorithms to solve the VLSI Floor plan issue. Simulated Annealing, tab search, ant colony optimization algorithm at last the genetic optimization algorithm are addressed in this article. |
