9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, −246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS
| Autor: | Xiang Gao, Cao-Thong Tu, Haisong Wang, Konstantinos Manetakis, Mustafa Yayla, Luns Tee, Sining Xiang, Fan Zhang, Olivier Burg, Li Lin, Randy Tsang, Wanghua Wu |
|---|---|
| Rok vydání: | 2016 |
| Předmět: |
Engineering
business.industry 020208 electrical & electronic engineering Electrical engineering 02 engineering and technology Phase detector 020202 computer hardware & architecture Phase-locked loop Voltage-controlled oscillator CMOS Sampling (signal processing) PLL multibit Phase noise 0202 electrical engineering electronic engineering information engineering Electronic engineering business Jitter |
| Zdroj: | ISSCC |
| DOI: | 10.1109/isscc.2016.7417963 |
| Popis: | High-performance phase-locked-loops (PLLs) are key building blocks for many modern ICs. The sub-sampling PLL proposed in [1] uses a reference clock REF to sample a high-frequency VCO and converts phase/timing error into voltage. The steep dv/dt slope of the VCO helps to realize a high phase-detection gain and greatly suppresses the noise of loop components succeeding the phase detector, leading to low in-band phase noise and good PLL Figure-Of-Merit (FOM). However, the original design in [1] is analog and limited to integer-N (int-N) operation. It is desirable to extend it to more versatile fractional-N (frac-N) mode, and to make it digital for greater flexibility and more advanced digital calibration. This work presents a new 28nm CMOS digital frac-N sampling PLL design that achieved 0.16ps rms jitter with 8.2mW and a state-of-the-art frac-N PLL FOM of −246.8dB. |
| Databáze: | OpenAIRE |
| Externí odkaz: |
|