A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application
| Autor: | Lee Chia-Fu, Chiu-Wang Lien, Jonathan Chang, Hon-Jarn Lin, Yu-Der Chih |
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| Rok vydání: | 2017 |
| Předmět: |
Bit cell
Hardware_MEMORYSTRUCTURES business.industry Computer science 020208 electrical & electronic engineering Electrical engineering 02 engineering and technology 021001 nanoscience & nanotechnology Chip Resistive random-access memory Non-volatile memory Flash (photography) Reliability (semiconductor) CMOS 0202 electrical engineering electronic engineering information engineering Macro 0210 nano-technology business |
| Zdroj: | A-SSCC |
| Popis: | Resistive RAM (ReRAM) is an attractive candidate for next generation embedded nonvolatile memory [1][2], with several advantages compared to conventional flash technology. First, ReRAM is a CMOS-compatible low temperature back-end of line (BEOL) memory. There is almost no mutual impact between ReRAM element and front-end CMOS devices during the wafer processing. Second, it only needs 2∼4 extra masks, resulting in lower chip cost compared to embedded flash. Third, its byte-alterability makes it capable of being used as a unified memory for storage of instruction code and real-time data. In this work, a 1.4Mb HfOx-based embedded ReRAM macro with 0.07um2 bit cell is fabricated in a 40nm CMOS process. A hybrid write-verify algorithm (HWVA) is used to tighten the resistance distribution and avoid over-write damage for achieving fast write and high endurance. Cycling test results show a write endurance of 106 cycles for the proposed HWVA. For low-power applications, a low power sensing scheme is presented for this 1.4Mb macro, achieving 100MHz read speed and 2.7mA/100MHz read current for 44-bits read operation. An area-efficient row-redundancy scheme and double-error-correction ECC are implemented for further improvement of yield and reliability. |
| Databáze: | OpenAIRE |
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