An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM
| Autor: | Rick Carter, Joseph Versaggi, Jack M. Higman, Randy W. Mann, Shesh Mani Pandey, Meixiong Zhao, Sanjay Parihar, Carl J. Radens, Qun Gao, Ankur Arya |
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| Rok vydání: | 2019 |
| Předmět: |
Very-large-scale integration
Hardware_MEMORYSTRUCTURES Materials science business.industry Drain-induced barrier lowering Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology 020202 computer hardware & architecture Hardware and Architecture Logic gate MOSFET Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Technology scaling Optoelectronics Static noise margin Static random-access memory Electrical and Electronic Engineering business Software Leakage (electronics) |
| Zdroj: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27:1819-1827 |
| ISSN: | 1557-9999 1063-8210 |
| DOI: | 10.1109/tvlsi.2019.2907594 |
| Popis: | A previously unrecognized vertical-extrinsic device in advanced 7-nm FinFET SRAM structures is identified and characterized for the first time. The ON-current for this vertical-extrinsic device is modulated by gate bias and exhibits a process-dependent threshold behavior. The ON-state of this parasitic device can exceed several nanoamperes and become the dominant mechanism in the static power of an SRAM array. Aggressively pushed ground rules used to achieve competitive SRAM density can result in exposure in FinFET-based SRAMs to this parasitic leakage path; n-Well and p-well dopant profiles, alignments, and dimensions must be carefully controlled to avoid this leakage mechanism in high-density FinFET SRAM arrays. |
| Databáze: | OpenAIRE |
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