Autor: |
Guido Torelli, J.F. Duque-Carrillo, J. Ramos, Jose L. Ausin |
Rok vydání: |
2013 |
Předmět: |
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Zdroj: |
Microelectronics Journal. 44:904-911 |
ISSN: |
0026-2692 |
DOI: |
10.1016/j.mejo.2012.12.011 |
Popis: |
This paper presents design considerations on CMOS limiting amplifiers to be used as basic building blocks for power-efficient logarithmic amplifiers. The impact of mismatches and device-level properties on sensitivity and gain-bandwidth product is discussed. To this end, a comparison of several types of low-voltage gain cell topologies is presented. Based on statistical (Monte Carlo) results, a high-sensitivity eight-stage limiting amplifier tolerant of process spreads and devices mismatches was designed in [email protected] CMOS technology to operate over dc to 20MHz bandwidth and experimentally evaluated. The proposed limiting amplifier draws [email protected] from a 2-V supply and achieves a voltage gain of 72dB. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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