Design and Verification of VHDL Code for FPGA Based Slave VME Interface Logic
Autor: | Nishi G Nampoothiri, Manju Mohan |
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Rok vydání: | 2014 |
Předmět: | |
Zdroj: | IOSR journal of VLSI and Signal Processing. 4:12-17 |
ISSN: | 2319-4200 2319-4197 |
DOI: | 10.9790/4200-04511217 |
Popis: | Versa Module Europa (VME) bus is used in various applications in order to ensure safety and security. VME64x based Real Time Computer (RTC) system with various types of Input / Output (I/O) hardware modules is being designed and developed for use in various safety critical and safety related Instrumentation & Control (I&C) systems. Analog Output Card (AOC) is one of the I/O hardware modules as part of VME64x RTC development. The AOC uses Field-Programmable Gate Array (FPGA) as VME bus system controller. This paper discusses the design and development of a VME64x bus controller so as to meet the required specifications correctly. |
Databáze: | OpenAIRE |
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