| Popis: |
To overcome the resolution limits of the current generation of steppers, mask makers are forced to include an ever-growing number of OPC features on 65 nm node masks. Although lithography techniques have improved significantlyin the last five years, they have not kept pace with the needs of 65 nm technology. To produce viable OPC features at the65 nm node, the etch process must be capable of accurately defining on the mask features as small as 100 nm. The etchmust also show reasonable linearity to prevent distortion of the primary features.To this end, a four factor, irregular fraction factorial design was performed using a 4 th generation mask etch system. Thefactors in this design include RIE power, RIE coupling effi ciency, ICP power, and pressure. These factors were selectedfor their influence on CD bias, CD uniformity, and CD linearity. The results of this design will be presented, along withan optimized solution. This solution is demonstrated on an asymmetric test pattern representative of logic or ASICdevices, as well as an evenly loaded pattern more representative of memory devices. |
