| Autor: |
C.M. How, C. Veriven, C. K. Ang, Norhayati Soin, M. H. Kamaruddin |
| Rok vydání: |
2019 |
| Předmět: |
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| Zdroj: |
2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA). |
| DOI: |
10.1109/ipfa47161.2019.8984760 |
| Popis: |
We conducted experiment to reduce the level defect density in 7.5nm thin SiO2 CMOS by improving the pre-cleaning of silicon surface before gate oxidation. Fast wafer level reliability monitoring is implemented using ramped voltage stress (RVS) where from the breakdown Weibull chart, the inclination point of intrinsic and extrinsic will give the measurement of defect density (unit is number of defect per cm2). We measured high defect density of >20 times the defect density target. Through systematic problem solving methodology, root cause was found to be due to ineffective cleaning method. With the additional SPM cleaning in the gate oxidation pre-clean step, defect density reduced by almost 95%. SPM chemistry reduces the surface roughness and also improves contaminations removal on the wafer surface prior to gate oxidation. Rougher interface of Si-SiO2 leads to early failure and lower TDDB. Inline silicon surface roughness check is not practical due to very small nature of embedded-type contaminants a rough silicon surface creates. In order to increase detection probability of micro-sized particles, a good reliability monitoring strategy using special test structures is implemented. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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