| Autor: |
Keng-Jan Hsiao, Tai-Cheng Lee |
| Rok vydání: |
2009 |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits. 44:2478-2487 |
| ISSN: |
0018-9200 |
| DOI: |
10.1109/jssc.2009.2024804 |
| Popis: |
A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 mm2 active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply. |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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