MCU-integrated PGA in 65nm CMOS with sub-1% gain error, 180ns acquisition window, and programmable output filter for motor control
| Autor: | Pavan K. Kulkarni, Aniruddha Roy, Nitin Agarwal, Poornima J. Boosi |
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| Rok vydání: | 2018 |
| Předmět: |
Computer science
020208 electrical & electronic engineering Successive approximation ADC 02 engineering and technology Filter (signal processing) law.invention Step response Noise CMOS law Logic gate 0202 electrical engineering electronic engineering information engineering Electronic engineering System on a chip Resistor |
| Zdroj: | ISCAS |
| Popis: | A high performance, low area (0.12mm2), MCU-integrated PGA, with gain range {3,6,12,24}, targeting a complete on-chip motor control solution in 65nm CMOS process is described. Its interpolation based analog gain trim allows design of resistor array with small parasitic, enabling fast settling of PGA (180ns for 12bit acquisition window and 400ns for 0.1 % step response to drive 12bit SAR ADC) across PVT. This design meets gain error of 0.5% for gain 3, 6, 12 and 0.75% for gain 24 across PVT. Additionally, switching noise, which is a nuisance in motor control world, is mitigated by providing an on-chip programmable R-bank which, along with on-board C, can deliver necessary noise filtering. Challenges for linear switch designs for R-programmability are solved with novel circuit approaches that made this PGA really usable. |
| Databáze: | OpenAIRE |
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