Autor: |
Juan Luis del Valle-Padilla, J. A. Reynoso-Hernandez, José Raúl Loo-Yau, J. E. Zuniga-Juarez |
Rok vydání: |
2009 |
Předmět: |
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Zdroj: |
2009 IEEE MTT-S International Microwave Symposium Digest. |
DOI: |
10.1109/mwsym.2009.5165837 |
Popis: |
In this paper a straightforward method to determine the parasitic gate resistance (R g ) of GaN FET is introduced. The method uses a simple linear regression to directly determine the value of R g without prior knowledge of the Schottky diode resistance R 0 and capacitance C 0 . Furthermore, the method requires only a single bias point with low DC current at the gate. In addition to this straightforward method, a reliable procedure for extracting the parasitic source inductance L S is also introduced. This procedure for extracting the source inductance is useful for GaN FET when the imaginary part of Z 12 is negative. The new method has been used successfully in the parasitic element characterization of power AlGaN/GaN HFETs. |
Databáze: |
OpenAIRE |
Externí odkaz: |
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