A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving −164-dBFS/Hz NSD
| Autor: | Haiyang Zhu, Shanthi Pavan, Jialin Zhao, Donald Paterson, Asha Ganesan, Victor Kozlov, Zexi Ji, Hajime Shibata, Sharvil Patil |
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| Rok vydání: | 2017 |
| Předmět: |
Signal processing
Settling time Computer science Noise spectral density 020208 electrical & electronic engineering Bandwidth (signal processing) 020206 networking & telecommunications Hardware_PERFORMANCEANDRELIABILITY 02 engineering and technology computer.file_format Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Oversampling Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering Hardware_REGISTER-TRANSFER-LEVELIMPLEMENTATION computer dBFS |
| Zdroj: | IEEE Journal of Solid-State Circuits. 52:3219-3234 |
| ISSN: | 1558-173X 0018-9200 |
| Popis: | An oversampled continuous-time (CT) pipeline ADC clocked at 9 GHz achieving 1.125-GHz bandwidth and −164 dBFS/Hz average small-signal noise density is presented. In contrast to traditional discrete-time (DT) pipeline ADCs, the system processes the signals in CT form throughout all the pipeline stages and thus sampling-induced artifacts such as aliasing and high-peak ADC driving current are mitigated. Despite the oversampled nature of the ADC, its digitization bandwidth is on par with that of traditional non-interleaved DT pipeline ADCs since CT signal processing is not constrained by settling time requirements. The ADC was fabricated in a 28-nm CMOS process technology and consumes 2.3 W. |
| Databáze: | OpenAIRE |
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