10nm high performance mobile SoC design and technology co-developed for performance, power, and area scaling
| Autor: | Ping Liu, Sung-Gun Kang, Jackie Yang, S. C. Song, Xiao-Yong Wang, Yanxiang Liu, Jedon Kim, Yandong Gao, Lixin Ge, Suh Youseok, Sam Yang, Jie Deng, Sung-Won Kim, Xiangdong Chen, Peijie Feng, Ken Rim, John Jianhong Zhu, Ming Cai, Chul-Yong Park, Da Yang, Jun Yuan, Hao Wang, Jihong Choi, Esin Terzioglu, P. R. Chidi Chidambaram, Jerry Bao, Paul Ivan Penzes |
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| Rok vydání: | 2017 |
| Předmět: |
010302 applied physics
Engineering Stress effects business.industry Electrical engineering 02 engineering and technology 01 natural sciences 020202 computer hardware & architecture Power (physics) Gigabit Logic gate 0103 physical sciences Hardware_INTEGRATEDCIRCUITS 0202 electrical engineering electronic engineering information engineering Electronic engineering Technology scaling Mobile telephony Design and Technology business Scaling |
| Zdroj: | 2017 Symposium on VLSI Technology. |
| DOI: | 10.23919/vlsit.2017.7998203 |
| Popis: | The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements. |
| Databáze: | OpenAIRE |
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