| Autor: |
S. W. Ho, Tai Chong Chai, Guruprasad Katti, Pei Siang Lim, Mian Zhi Ding, Surya Bhattacharya, Daniel Ismail Cereno |
| Rok vydání: |
2014 |
| Předmět: |
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| Zdroj: |
2014 IEEE 16th Electronics Packaging Technology Conference (EPTC). |
| DOI: |
10.1109/eptc.2014.7028352 |
| Popis: |
In this paper, the fabrication process and results of 2.5D through silicon interposer (TSI) package using polymer based RDL and chip-on-wafer (CoW) stacking-first approach is presented. The through silicon interposer is fabricated on a 300 mm silicon substrate with Cu filled vias of aspect ratio of 1:10. Fine-pitch Cu RDL using semi-additive process and polymer based dielectric is used to form the 3 layer of rerouting layer on front-side. Chips with micro-bumps are flip chip assembled onto the under bump metallization (UBM) of the 12 inch interposer substrate using thermal compression bonding via chip-on-wafer (CoW) format on the thick interposer substrate A wafer level molding process is used to form the over-mold encapulation over the assembled chips. The over-mold encapsulation is mechanically thinned down to reduce the warpage of the molded interposer and temporary bonded to a silicon carrier. Mechanical-grinding and chemical mechanical polishing (CMP) is used to expose the Cu vias from the backside. Cu-RDL process is used to form the backside re-routing layer and UBM for solder bumps. The completed interposer wafer is then diced into singulated packages for assembled to printed circuit board (PCB). |
| Databáze: |
OpenAIRE |
| Externí odkaz: |
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