A 20-MS/s to 40-MS/s Reconfigurable Pipeline ADC Implemented With Parallel OTA Scaling
| Autor: | M Corsi, Bertan Bakkaloglu, J Fattaruso, Kailash Chandrashekar |
|---|---|
| Rok vydání: | 2010 |
| Předmět: |
Engineering
business.industry Transistor Bandwidth (signal processing) Analog-to-digital converter law.invention Capacitor CMOS law Hardware_INTEGRATEDCIRCUITS Operational amplifier Electronic engineering Laser power scaling Hardware_ARITHMETICANDLOGICSTRUCTURES Electrical and Electronic Engineering business DC bias |
| Zdroj: | IEEE Transactions on Circuits and Systems II: Express Briefs. 57:602-606 |
| ISSN: | 1558-3791 1549-7747 |
| DOI: | 10.1109/tcsii.2010.2050948 |
| Popis: | A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18-μm CMOS process and occupies a die area of 1.9 mm2. |
| Databáze: | OpenAIRE |
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