| Popis: |
Coding corrector of errors is one of the most vital and emerged system in telecommunication field.In this paper, we propose an efficient new embedded Chien Search block for RS decoder. However, it adopts a factorization of error locator polynomial. The proposed design is developed by using hardware description language (HDL), after that, simulated and verified Quartus development software.To test the performances of the new developed design, minimization rate (Number of minimized logic gates) and BER criteria were used.Simulation results show the effectiveness of the proposed design than the basic. First, because it minimizes the number of logic gates and hardware resources. Therefore, a reduction of the power consumption with a minimization’s rate that can attain approximately 40 % compared to the basic algorithm. Further, because it reaches a lower bit error rate. |
